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MRF49XA
3.18.1
INTERRUPT MODE
3.18.2
POLLING MODE
The user can define the FIFO interrupt level (the
number of received bits) which generates the FINT
when the level is exceeded. In this case, the Status bits
report the changed FIFO status.
When the FSEL signal is low, the FIFO output is
connected directly to the SDO pin and its contents are
clocked out by the SCK pin. Set the FIFO interrupt level
to 1. In this case, as long as FINT indicates received
bits in the FIFO, the microcontroller continues to take
the bits away. When FINT goes low, no more bits need
to be taken.
An SPI read command (Receiver FIFO Read
Command) is also available to read out the contents of
the FIFO. See Figure 3-19 for a simple receiver FIFO
read, in Polling mode, on SPI lines.
TABLE 3-4:
RECEIVE PIN FUNCTION VS . OPERATION MODE
Mode
Receive
Bit Setting
FIFOEN = 0
FIFOEN = 1
Function
Receiver FIFO Disabled
Receiver FIFO Enabled
Pin 6
RX Data Output
FSEL Input
Pin 7
RX Data Clock Output
FINT Output
(RX data FIFO can be
accessed)
FIGURE 3-19:
FIFO READ EXAMPLE WITH FINT POLLING
CS
0
1
2
3
4
SCK
FSEL
FIFO Read Out
SDO
FIFO OUT
FO + 1
FO + 2
FO + 3
FO + 4
FINT
The registers associated with reception are:
Note:
During FIFO access, f SCK cannot be
higher than f ref /4, where f ref is the crystal
oscillator frequency. If the duty cycle of
the clock signal is not 50%, the shorter
period of the clock pulse should be at
least 2/f ref .
?
?
?
?
?
STSREG (see Register 2-1 )
GENCREG (see Register 2-2 )
RXCREG (see Register 2-7 )
FIFORSTREG (see Register 2-10 )
PMCREG (see Register 2-13 )
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 71
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